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upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 1 single 12v input supply dual regulator - synchronous-buck-pwm and linear-regulator controller ? ? ? ? ? operate with single 12v supply ? ? ? ? ? self-regulated 9v drive voltage ? ? ? ? ? integrated boot diode ? ? ? ? ? provide two regulated voltages ? ? ? ? ? one synchronous-rectified buck controller ? ? ? ? ? one linear controller ? ? ? ? ? both controllers drive n-channel mosfets ? ? ? ? ? smaller converter size ? ? ? ? ? excellent output voltage regulation ? ? ? ? ? 1.5% for buck controller ? ? ? ? ? 2% for linear controller ? ? ? ? ? simple single-loop control design ? ? ? ? ? voltage-mode pwm control ? ? ? ? ? fast transient response ? ? ? ? ? high-bandwidth error amplifier ? ? ? ? ? lossless, programmable overcurrent protection ? ? ? ? ? uses lower mosfet r ds(on) ? ? ? ? ? adjustable frequency from 150khz to 1mhz ? ? ? ? ? internal soft start for both outputs ? ? ? ? ? under voltage protection for both outputs including soft start cycle ? ? ? ? ? sop-14 and qfn3x3-16 packages ? ? ? ? ? rohs compliant and 100% lead free r e b m u n r e d r oe p y t e g a k c a pk r a m e r 4 1 s 1 6 1 6 p u4 1 - p o s q 1 6 1 6 p u6 1 - 3 x 3 n f q ? ? ? ? ? power supplies for microprocessors or subsystem power supplies ? ? ? ? ? cable modems, set top boxes, and dsl modems ? ? ? ? ? industrial power supplies; general purpose supplies ? ? ? ? ? 12v input dc-dc regulators ? ? ? ? ? low-voltage distributed power supplies general description a pplications ordering information features note: upi products are compatible with the current ipc/ jedec j-std-020 and rohs requirements. they are 100% matte tin (sn) plating and suitable for use in snpb or pb- free soldering processes. the UP6161 integrates a high performance synchronous- rectified buck controller and a linear-regulator controller. this part works with a single +12v supply voltage and delivers two high quality output voltages for both processing unit and memory unit. an internal linear regulator provides optimum 9v drive voltage for efficiency and thermal management. the buck controller features internal mosfet drivers that supports bootstrapped voltage for high efficiency power conversion. the bootstrap diode is built-in to simplify the circuit design and minimize external part count. it incorporates simple, single feedback loop, voltage-control with fast transient response. the linear controller drives an external n-channel mosfet with under voltage protection during both soft start and normal operation. other features include adjustable operation frequency, internal soft start, under voltage protection, adjustable over current protection and shutdown function. with the above function, this part provides customers a compact, well protected and cost-effective solution. this part is available in sop-14 and qfn3x3 -16l packages.
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 2 typical application circuit pin configuration phase pvcc9 ugate boot pgnd lgate rt/dis comp fb 1 2 3 411 12 13 14 sop-14 vcc9 vcc12 ldrv lfb agnd 5 6 78 9 10 1 2 3 4 16 15 14 13 pgnd phase pvcc9 ugate boot pgnd lgate rt/dis comp fb vcc9 vcc12 ldrv lfb agnd 12 11 10 9 5 6 7 8 vcc12 pgnd qfn3x3 C 16l UP6161s14 1 7 6 8 14 boot ugate gnd lgate phase comp enable disable v in1 v out1 5 2 9 4 3 vcc12 pvcc9 vcc9 ldrv lfb rt/dis# fb 13 11 13 pgnd 10 v in2 v out2 +12v r1 r2
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 3 functional block diagram pvcc9 lgate phase ugate boot vcc5 internal regulator internal regulator soft start gate control logic oscillator enable & protection logic por & reference pvcc9 pgnd gnd rt/dis comp ldrv lfb fb vcc12 vcc9 ss1 ss2 ss3 0.6v 0.6v 0.8v ss2 0.8v ss3 0.4v v ocp ss1
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 4 . o n n i p n i p e m a n n o i t c n u f n i p p o sn f q 15 1t o o b y l p p u s p a r t s t o o b c r o t i c a p a c p a r t s t o o b e h t t c e n n o c . r e v i r d e t a g r e p p u g n i t a o l f e h t r o f t o o b r o t i c a p a c p a r t s t o o b e h t . t i u c r i c p a r t s t o o b a m r o f o t n i p e s a h p e h t d n a n i p t o o b n e e w t e b r o f s e u l a v l a c i p y t . t e f s o m r e p p u e h t n o n r u t o t e g r a h c e h t s e d i v o r pc t o o b f u 1 . 0 m o r f e g n a r c t a h t e r u s n e . f u 7 4 . 0 o t t o o b . c i e h t r a e n d e c a l p s i 26 1s i d / t r . e l b a s i d p i h c d n a g n i t t e s y c n e u q e r f f o y c n e u q e r f n o i t a r e p o e h t s t e s d n g o t r o t s i s e r a . s r o t a l u g e r r a e n i l d n a k c u b h t o b s e l b a s i d d n g o t n i p s i h t g n i l l u p . r e t r e v n o c k c u b e h t r o f 31 p m o c . t u p t u o r e i f i l p m a r o r r e g n i t r e v n i - n o n e h t d n a ) a e ( r e i f i l p m a r o r r e e h t f o t u p t u o e h t s i s i h t e h t e t a s n e p m o c o t n i p b f e h t h t i w n o i t a n i b m o c n i n i p s i h t e s u . r o t a r a p m o c m w p e h t f o t u p n i . r e t r e v n o c k c u b e h t f o p o o l k c a b d e e f l o r t n o c - e g a t l o v 42 b f . r e t r e v n o c k c u b r o f e g a t l o v k c a b d e e f . r e i f i l p m a r o r r e e h t o t t u p n i g n i t r e v n i e h t s i n i p s i h t n i n i p s i h t e s u . e g a t l o v n o i t a l u g e r e h t t e s o t d e s u s i d n g o t t u p t u o e h t m o r f r e d i v i d r o t s i s e r a e h t f o p o o l k c a b d e e f l o r t n o c e g a t l o v e h t e t a s n e p m o c o t n i p p m o c e h t h t i w n o i t a n i b m o c . r e t r e v n o c 53 v r d l . r o t a l u g e r r a e n i l r o f t u p t u o r e v i r d r o t a l u g e r r a e n i l e h t r o f e g a t l o v e t a g e h t s e d i v o r p n i p s i h t r a e n i l a m r o f o t t e f s o m l e n n a h c - n l a n r e t x e n a f o e t a g e h t o t n i p s i h t t c e n n o c . r o t s i s n a r t s s a p . r o t a l u g e r 64 b f l . r o t a l u g e r r a e n i l r o f e g a t l o v k c a b d e e f . r e i f i l p m a r o r r e e h t o t t u p n i g n i t r e v n i e h t s i n i p s i h t . e g a t l o v n o i t a l u g e r e h t t e s o t d e s u s i d n g o t t u p t u o e h t m o r f r e d i v i d r o t s i s e r a 75 d n g a . c i e h t r o f d n u o r g l a n g i s s i h t e i t . n i p s i h t o t t c e p s e r h t i w d e r u s a e m e r a s l e v e l s e g a t l o v l l a . e l b a l i a v a n o i t c e n n o c e c n a d e p m i t s e w o l e h t h g u o r h t e n a l p / d n a l s i d n u o r g e h t o t n i p 88 , 72 1 c c v . e g a t l o v y l p p u s r o t a l u g e r v 9 l a n r e t n i e h t s e c r u o s t i ; c i e h t r o f n i p y l p p u s r e w o p e h t s i s i h t g n i s s a p y b y l l a c o l r o f d e r i u q e r s i r o t i c a p a c c i m a r e c f u 1 m u m i n i m a . s r e v i r d e t a g e h t o t d e s u . e g a t l o v t u p n i e h t 99 9 c c v . 9 c c v y l l a c i s y h p r o t i c a p a c c i m a r e c f u 1 m u m i n i m a . c i e h t r o f t n e r r u c s a i b s e i l p p u s n i p s i h t . e g a t l o v t u p n i e h t g n i s s a p y b y l l a c o l r o f d e r i u q e r s i c i e h t r a e n 0 10 19 c c v p . 9 c c v p r e w o p d e r i u q e r t n e r r u c s e d i v o r p t i . r o t a l u g e r r a e n i l v 9 l a n r e t n i e h t f o t u p t u o e h t s i s i h t r o t i c a p a c c i m a r e c f u 1 m u m i n i m a . r e t r e v n o c k c u b f o s t e f s o m l e n n a h c - n g n i v i r d r o f . e g a t l o v t u p n i e h t g n i s s a p y b y l l a c o l r o f d e r i u q e r s i c i e h t r a e n y l l a c i s y h p 1 11 1e t a g l . t u p t u o r e v i r d e t a g r e w o l s i n i p s i h t . t e f s o m r e w o l f o e t a g e h t o t n i p s i h t t c e n n o c r e w o l e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b d e r o t i n o m . f f o n r u t s a h t e f s o m 2 12 1 , 6d n g p . c i e h t r o f d n u o r g r e w o p 3 13 1e s a h p . e d o n h c t i w s e s a h p f o n i a r d e h t d n a t e f s o m r e p p u e h t f o e c r u o s e h t o t n i p s i h t t c e n n o c e h t r o t i n o m o t d n a , r e v i r d e t a g u e h t r o f k n i s e h t s a d e s u s i n i p s i h t . t e f s o m r e w o l e h t d e r o t i n o m o s l a s i n i p s i h t . n o i t c e t o r p t n e r r u c r e v o r o f t e f s o m r e w o l e h t s s o r c a p o r d e g a t l o v s a h t e f s o m r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b e v i t a g e n e c u d e r o t d e d n e m m o c e r s i d n u o r g d n a n i p s i h t n e e w t e b e d o i d y k t t o h c s a . f f o d e n r u t . m e t s y s y l p p u s r e w o p a n i n o m m o c s i h c i h w e g a t l o v t n e i s n a r t 4 14 1e t a g u . t u p t u o r e v i r d e t a g r e p p u s i n i p s i h t . t e f s o m r e p p u f o e t a g e h t o t n i p s i h t t c e n n o c r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b d e r o t i n o m . f f o d e n r u t s a h t e f s o m d a p d e s o p x e . c i e h t r o f d n u o r g r e w o p d e r e d l o s l l e w e b d l u o h s d a p d e s o p x e s i h t . y l n o e g a k c a p n f q r o f . d n u o r g e h t d a p d e s o p x e e h t t c e n n o c . n o i t c u d n o c t a e h e v i t c e f f e r o f b c p o t functional pin descriptio n
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 5 power on reset with typical rising threshold level as 7.5v. all the three supply inputs require minimum 1uf ceramic capacitors for local bypassing. place the bypass capacitors physically near the ic. no external bypass capacitor is required for filtering the vcc5 voltage. bootstrap circuitry the UP6161 integrates mosfet gate drives that are powered from the pvcc9 pin and support 12v+12v driving capability. a bootstrap diode is embedded to facilitates pcb design and reduce the total bom cost. connect a ceramic bootstrap diode between boot and phase pins to form a bootstrap circuit for providing charge to turn on/off the upper mosfet. no external schottky diode is required. converters that consist of UP6161 feature high efficiency without special consideration on the selection of mosfets. chip enable and frequency setting the rt/dis is a multifunctional pin: chip shutdown and frequency setting. pulling low this pin to gnd by an open drain/collector transistor shuts down the UP6161 and disables both buck and linear controllers. the switching frequency is set by a resistor connecting to the rt/dis pin as: 74000 r 23500000 f rt osc + = (hz) figure 2 shows the dependence between the resistor chosen and the resulting switching frequency. 100 1000 10 100 1000 r rt (kohm) switching frequency (khz ) figure 2. switching frequency vs. r rt soft start once por is acknowledged and rt/dis pin is released, functional description the UP6161 integrates a high performance synchronous- rectified buck controller and a linear-regulator controller. this part works with a single +12v supply voltage and delivers two high quality output voltages for both processing unit and memory unit. an internal linear regulator provides optimum 9v drive voltage for efficiency and thermal management. the buck controller features internal mosfet drivers that supports 12v + 12v bootstrapped voltage for high efficiency power conversion. the bootstrap diode is built-in to simplify the circuit design and minimize external part count. it incorporates simple, single feedback loop, voltage-control with fast transient response. the linear controller drives an external n-channel mosfet with undervoltage protection during both softstart and normal operation. other features include adjustable operation frequency, internal softstart, undervoltage protection, adjustable overcurrent protection and shutdown function. supply voltage the UP6161 is designed to work with a single supply rail. it integrates two linear regulators providing optimal supply voltages for gate drivers and control circuitry respectively as shown in figure 1. the 9v linear regulator generates 9v pvcc9 for gate drives achieving optimum balance between efficiency and thermal management. the 5v linear regulator works with vcc9 input generates vcc5 for internal control circuitry. if 12v driving voltage is preferred, simply connect +12v to the pvcc9 pin and let vcc12 open. 9v linear regulator 5v linear regulator control circuitry gate drivers por monitoring vcc12 pvcc9 vcc9 UP6161 +12v figure 1. supply voltage configuration both pvcc9 and vcc9 are continuously monitored for
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 6 the UP6161 initiates its digital soft start cycle to prevent surge current from power supply input during turn on (referring to the functional block diagram). the error amplifiers are three-input devices. reference voltage v ref or the internal soft start voltage ss2/ss3 whichever is smaller dominates the behavior of the non-inverting inputs of the error amplifiers. ss2/ss3 internally ramps up to 0.8v in 4096 cycles of the internal oscillator frequency after the after the softstart cycle is initiated. take 600khz switching frequency for example (1.67us per cycle), the ramp-up time is about 6.8ms. accordingly, the output voltages follow the soft start signals ss2/ss3 and linearly ramp up to their final level, resulting minimum inrush current from input voltage. the ss2/ss3 signals keep ramping up after it exceeds the internal 0.8v reference voltages. however, the internal 0.8v reference voltages takes over the behavior of error amplifier after ss > v ref . when the ss2/ss3 signal climb to its ceiling voltage (5v), the UP6161 claims the end of softstart cycle and enable the under voltage protection of the output voltages. figure 3 shows a typical start up interval for UP6161 where the rt/dis pin has been released from a grounded (system shutdown) state. note the ldo output voltage (lvo) starts ramping up only after the pwm output voltage (svo) is within regulation. rt/dis (1v/div) svo (0.5v/div) lvo (0.5v/div) phase (10v/div) time (5ms/div) figure 3. softstart behavior. power input detection the UP6161 detects phase voltage for the present of power input when the ugate turns on the first time. if the phase voltage does not exceed 2.0v when the ugate turns on, the UP6161 asserts that power input in not ready and stops the softstart cycle. however, the internal ss continues ramping up to 5vdd. another softstart is initiated after ss ramps up to 5vdd. the hiccup period is about 8ms. figure 4 shows the start up interval where v in does not present initially. v in (5v/div) svo (0.5v/div) lvo (0.5v/div) lgate (10v/div) time (5ms/div) figure 4. softstart where v in does not present initially. output voltage selection the output voltage can be programmed to any level between the 0.8v internal reference, up to the 80% of v in supply. the lower limitation of output voltage is caused by the internal reference. the upper limitation of the output voltage is caused by the maximum available duty cycle (80% typical). this is to leave enough time for overcurrent detection. output voltage out of this range is not allowed. a voltage divider sets the output voltage (refer to the typical application circuit on page 1 for detail). in real applications, choose r2 in 100 ~ 10k range and choose appropriate r1 according to the desired output voltage. 2 r 2 r 1 r v 8 . 0 2 r 2 r 1 r v v ref out + = + = overcurrent protection (ocp) the UP6161 detects voltage drop across the lower mosfet (v phase ) for overcurrent protection when it is turned on. if v phase is lower than the user-programmable voltage v ocp , the UP6161 asserts ocp and shuts down the converter. the ocp level can be calculated according the on- resistance of the lower mosfet used. ) on ( ds ocp ocp r v i ? = (a) connecting a resistance from lgate to gnd selects the functional description
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 7 functional description appropriate v ocp as shown in table 1. also shown in table 1 is ocp level if a lower mosfet with 10m r ds(on) is used. when programming the ocp level, take into consideration the conditions that affect r ds(on) of the lower mosfet, including operation junction temperature, gate driving voltage and distribution. consider the r ds(on) at maximum operation temperature and lowest gate driving voltage. table 1. ocp level selection r p c o ( )n e p ok 2 4k 4 2k 0 1 v p c o ) v m (5 7 3 -0 0 3 -5 2 2 -0 5 1 - i p c o ) a (5 . 7 35 25 . 2 25 1 another factor should taken into consideration is the ripple of the inductor current. the current near the valley of the ripple current is used for ocp, resulting the averaged ocp level a little higher than the calculated value. output under voltage protection of linear regulator the ldrv and lfb voltages are monitored during both softstart and normal operation for output under voltage protection. the UP6161 asserts uvp if the error amplifier saturates, ldrv goes to ceiling high and lfb voltage is lower than 0.6v for 10us. this demands v cc12 > (v out + v th + 1v) where v th is the threshold voltage of the external n-channel mosfet. this is to ensure that the output voltage can follow the softstart signal and will not saturate the error amplifier. that means a low threshold voltage mosfet is required for low v cc12 applications. this also demands that v in2 should be ready before the soft start cycle is initiated. the UP6161 disables the output voltages upon the triggering of uvp. the UP6161 repeats the softstart cycle if the output under voltage is not removed.
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 8 supply input voltage, vcc12 (note 1) -------------------------------------------------------------------------------------------- -0.3v to +15v phase to gnd dc ---------------------------------------------------------------------------------------------------------------------------- --------- -1v to 15v < 200ns ----------------------------------------------------------------------------------------------------------------------- ----- -3v to 30v boot to phase ----------------------------------------------------------------------------------------------------------------- ----------- -0.3v to +15v ugate to phase ------------------------------------------------------------------------------------------------ -0.3v to (boot - phase +0.3v) pvcc9, vcc9, ldrv ----------------------------------------------------------------------------------------------------- -0.3v to vcc12 + 0.3v lgate ------------------------------------------------------------------------------------------------------------------------ -0.3v to + (pvcc9 + 0.3v) other pins -------------------------------------------------------------------------------------------------------------------- ------------------ -0.3v to +6v storage temperature range ------------------------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature ------------------------------------------------------------------------------------------------------------------------------- ----- 150 o c lead temperature (soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260 o c esd rating (note 2) hbm (human body mode) --------------------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------------------------------------------- 2 00v package thermal resistance (note 3) ja sop-14 ---------------------------------------------------------------------------------------------------------------------- -------- 120 c/w jc qfn3x3-16 ------------------------------------------------------------------------------------------------------------------- ---------- 5 o c/w ja qfn3x3-16 ------------------------------------------------------------------------------------------------------------------- --------- 68 o c/w power dissipation, p d @ t a = 25 c sop-14 ------------------------------------------------------------------------------------------------------------------------ ----------------------- 0.83w qfn3x3-16 --------------------------------------------------------------------------------------------------------------------- --------------------- 1.47w operating junction temperature range (note 4) ------------------------------------------------------------------------ -40 c to +125 c operating ambient temperature ra nge -------------------------------------------------------------------------------------- -40 c to +85 c supply input voltage, v cc12 ----------------------------------------------------------------------------------------------------------- +10.8v to 13.2v r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u t u p n i y l p p u s e g a t l o v y l p p u sv 2 1 c c 8 . 0 1- -2 . 3 1v t n e r r u c y l p p u si 2 1 c c v ; n e p o e t a g l d n a e t a g u 2 1 c c , v 2 1 = g n i h c t i w s - -4- -a m t n e r r u c y l p p u s t n e c s e i u qi q _ 2 1 c c v b f v = f e r g n i h c t i w s o n , v 1 . 0 +- -3- -a m e g a t l o v t u p n i r e w o pv 1 n i 0 . 32 . 3 1v t e s e r n o r e w o p d l o h s e r h t r o p 2 1 c c vv h t r 2 1 c c - -7 . 8- -v d l o h s e r h t r o p 9 c c v pv h t r 9 c c v g n i s i r 9 c c v = 9 c c v p- -5 . 78v s i s e r e t s y h r o pv s y h 9 c c g n i l l a f 9 c c v = 9 c c v p- -8 . 0- -v (v cc12 = 12v, t a = 25 o c, unless otherwise specified) a bsolute maximum ratin g thermal informatio n recommended operation conditions electrical characteristics
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 9 r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u o d l 9 c c v p e g a t l o v t u p t u o 9 c c v p9 c c v pv 2 1 c c v 2 1 =- -0 . 9- -v t r a t s t f o s d n a r o t a l l i c s o y c n e u q e r f g n i h c t i w sf c s o r t r k 3 . 5 4 = 0 4 50 2 60 0 7z h k e d u t i l p m a h t o o t w a s v c s o - -4- -v l a v r e t n i t r a t s t f o st s s f c s o z h k 0 2 6 =- -8 . 6- -s m e g a t l o v e c n e r e f e r m w p r o f e g a t l o v e c n e r e f e rv f e r 8 8 7 . 08 . 02 1 8 . 0v o d l r o f e g a t l o v e c n e r e f e rv f e r 4 8 7 . 08 . 06 1 8 . 0v r e l l o r t n o c k c u b r o f r e i f i l p m a r o r r e n i a g c d p o o l n e p oa o n g i s e d y b d e e t n a r a u g5 50 7- -b d t c u d o r p h t d i w d n a b - n i a gp w b gn g i s e d y b d e e t n a r a u g- -0 1- -z h m e t a r w e l sr sn g i s e d y b d e e t n a r a u g46- -s u / v e g a t l o v t u p t u o h g i h p m o cv h _ p m o c - -7 . 4- -v e g a t l o v t u p t u o w o l p m o cv l _ p m o c - -6 . 0- -v t n e r r u c e c r u o s h g i h p m o ci h _ p m o c - -8 . 2 -- -a m v ( l e v e l e g a t l o v r e d n u b f v / f e r )v p v u 0 75 70 8% s r e v i r d e t a g r e l l o r t n o c k c u b t n e r r u c e c r u o s e t a g ui c r s _ g u v p c c v , v 9 = t o o b v - g u v 8 =- -5 . 1 -- -a e c n a d e p m i t u p t u o k n i s e t a g ur k n s _ g u v p c c i , v 9 = g u a m 0 0 1 =- -24 t n e r r u c e c r u o s e t a g li c r s _ g l v p c c v , v 9 = g l v 1 =- -5 . 1 -- -a e c n a d e p m i t u p t u o k n i s e t a g lr k n s _ g l v p c c i , v 9 = g l a m 0 0 1 =- -24 e l c y c y t u d m u m i x a m 0 75 70 8% r e l l o r t n o c r o t a l u g e r - r a e n i l n i a g c d p o o l n e p oa o n g i s e d y b d e e t n a r a u g5 50 7- -b d t c u d o r p h t d i w d n a b - n i a gp w b gn g i s e d y b d e e t n a r a u g- -2- -z h m e t a r w e l sr sn g i s e d y b d e e t n a r a u g24- -s u / v t n e r r u c s a i b b fi b f v b f v 8 . 0 =- -1 0 . 01a u e g a t l o v t u p t u o h g i h v r d lv h _ v r d l v 9 = c c v p- -5 . 80 . 9v e g a t l o v t u p t u o w o l v r d lv l _ v r d l v 9 = c c v p- -0 . 05 . 0v t n e r r u c e c r u o s h g i h v r d li h _ v r d l 5- -- -a m t n e r r u c k n i s w o l v r d li l _ v r d l 5- -- -a m v ( l e v e l e g a t l o v r e d n u b f l v / f e r )v p v u l a n i m o n f o t n e c r e p0 75 70 8% electrical characteristics
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 10 note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. electrical characteristics r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u n o i t c e t o r p d l o h s e r h t t n e r r u c r e v ov e s a h p r e t a g l n e p o =- -5 7 3 -- -v m d l o h s e r h t e l b a n ev s i d / t r 3 . 04 . 05 . 0v
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 11 rt/dis (1v/div) phase (10v/div) ldrv (2v/div) sv out (0.5v/div) phase (10v/div) i out (10a/div) lgate (5v/div) phase (5v/div) ugate (5v/div) ugate-phase (5v/div) lgate (5v/div) phase (5v/div) ugate (5v/div) ugate-phase (5v/div) vcc12 (5v/div) sv out (0.5v/div) lv out (0.5v/div) pvcc9 (5v/div) sv out (0.5v/div) lv out (0.5v/div) rt/dis (0.5v/div) phase (10v/div) typical operation characteristics power on waveforms 5ms/div turn on waveforms 2.5ms/div gate waveforms 25ns/div gate waveforms 25ns/div trun off waveforms 5us/div over current protection 10ms/div
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 12 7 7.5 8 8.5 9 9.5 10 8101214 typical operation characteristics pvcc9 voltage vs. vcc12 voltage vcc12 voltage (v) pvcc9 voltage (v) switching frequency vs. r rt r rt (k ) switching frequency (khz) pvcc9 voltage vs. temperature junction temperature ( o c) vcc12 = 12v pvcc9 output voltage (v) dc/dc output voltage vs. temperature junction temperature ( o c) dc/dc output voltage variation (%) switching frequency vs. temperature junction temperature ( o c) switching frequency variation (%) ldo output voltage vs. temperature junction temperature ( o c) ldo output voltage variation (%) -4 -3 -2 -1 0 1 2 -50 0 50 100 150 -1.5 -1.3 -1.1 -0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 -50 0 50 100 150 9 9.01 9.02 9.03 9.04 9.05 9.06 9.07 -50 0 50 100 150 -1 -0.7 -0.4 -0.1 0.2 0.5 -50 0 50 100 150 100 1000 10 100 1000
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 13 a pplication information this page is intentionally left blank and will be updated when the silicon data is available.
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 14 note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions no not include mold flash or protrusions. mold flash or protrusions shell not exceed 0.15mm. package informatio n sop-14 package 0.32 - 0.52 8.50 - 8.75 5.80 - 6.20 7.62 bsc 0.10 - 0.25 0.18 - 0.25 0.41 - 0.89 0.20 bsc 8.00 min 1.85 ref 0.76 ref 1.27 ref 1.27 bsc 3.80 - 4.00 6.15 ref 4.00 min recommended solder pad layout 1.75 max 1.45 - 1.60
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6161-ds-p0001 UP6161 preliminary 15 note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions no not include mold flash or protrusions. mold flash or protrusions shell not exceed 0.15mm. package informatio n qfn3x3 - 16l package 2.90 - 3.10 2.90 - 3.10 0.35 - 0.45 1.50 - 1.75 0.18 - 0.30 0.50 bsc 1.50 - 1.75 3.45 - 3.55 2.10 - 2.20 1.60 - 1.70 0.20 - 0.30 0.50 bsc 0.80 - 1.00 0.20 - ref 0.00 - 0.05 1 5 9 13 pin 1 mark (note 6) bottom view - exposed pad recommended solder pitch and dimensions

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